Multiply add sequences, in which the product of two operands is added to a third operand, i.e., (A*B+C), occur frequently in FP intensive applications. An FP multiply add sequence can be executed as a 2-input or simple FP multiplication to generate A*B followed by a simple FP addition to sum A*B and C. A reduction in the total number of clock cycles required to produce the result can be achieved with a 3-input FP ALU that includes an FP multiplier receiving the first two inputs and an FP adder receiving the third input and the output of the FP multiplier. Although the two approaches should yield the same result, discrepancies may arise because the output of the 2-input FP multiplier used in the simple or 2-cycle multiply add sequence is rounded under long standing floating point protocols.